1. Field of the Invention
The present invention relates generally to improvements in a pulse justification (stuffing) synchronous TDM (time division multiplexing), and more specifically to a method and arrangement of specifying a leading time slot of a data stream by detecting a pointer involved in each demultiplexed channel information in a TDM digital transmission system.
2. Description of the Prior Art
It is known in the art to determine the location of the byte (viz., time slot) where data begins by means of detecting a pointer involved in demultiplexed channel information. The pointer further carries the pointer value and frequency stuffing information of positive, negative or zero justification. The pointer value indicates the offset between the pointer and the first byte of the data.
Before turning to the present invention it is deemed advantageous to discuss, with reference to FIGS. 1 and 2, a known pointer processing arrangement which determines the location of a time slot of the data whose information length is previously determined and used as a virtual container, for example.
The arrangement shown in FIG. 1 is illustrated as including only three demultiplexed data channels 10a-10c for the sake of simplifying the drawing and the descriptions thereof. Three pointer detectors 12a-12c are provided in the data channels 10a-10c and are respectively arranged to receive three channel data Da-Dc. The arrangement of FIG. 1 further includes three essentially identical justification discriminators 14a-14c, three essentially identical selectors 16a-16c, three essentially identical pointer offset counters 18a-18c and three essentially identical comparators 20a-20c, all of which are respectively provided for the three channels 10a-10c.
A pointer offset generator 22 is provided to receive three timing signals 22a-22c and a clock CLK. The timing signals 22a, 22b and 22c are respectively a zero, negative and positive justification timing signals. The generator 22 produces three kinds of clocks, viz., a zero justification clock 24a, a negative justification clock 24b and a positive justification clock 24c.
For the sake of simplifying the description, only the operations of one of the channels, viz., channel 10a, will be described with reference to the blocks 12a, 14a, 16a, 18a, 20a and 22 associated with said channel 10a. The same discussions hold for the remaining channels 10b and 10c.
The pointer detector 12a is supplied with the channel data Da and extracts a pointer (10 bits merely by way of example) included therein. The pointer thus derived is applied to the justification discriminator 14a which compares a preceding pointer memorized therein with the newly applied pointer, and then produces a justification signal 26a and the previously memorized pointer value denoted by 28a. The pointer offset generator 22 supplies the selector 16a with the three clocks 24a-24c. The selector 16a selects one of the clocks 24a-24b depending on the justification signal 26a, and applies the selected clock 17a to the pointer offset counter 18a which issues the pointer offset 19a by counting the applied clock. Lastly, the comparator 20a receives the pointer offset from the counter 18a and the pointer value from the justification discriminator 14a and compares the same. The comparator 20a generates an output 30a which indicates the location of the byte(s) where the data (e.g., a virtual container) begins.
Similarly, the comparators 20b, 20c respectively generate outputs 30b, 30c similar to the output 30a in the same manner as mentioned above. The justification discriminator 14b, 14c also produce the signals 26b, 28b, 26c and 28c which respectively correspond to the counterparts 26a, 28a as mentioned above.
The operations of the FIG. 1 arrangement will further be described with reference to a timing chart schematically shown in FIG. 2. As in the above, only the operations of the channel 10a will be given in that those of the other channels 10b, 10c are exactly equal thereto. The data and signals whose timing charts are depicted in FIG. 2, appear in the FIG. 1 arrangement and thus are denoted by the reference numerals and/or characters utilized in FIG. 1.
As illustrated in FIG. 2, the data Da transmitted over the channel 10a includes two pointers P and three time slots 50, 52 and 54 which denote respectively the time slots for zero, negative and positive justifications. No data is located or available at the time slots 50, 52 and 54. Therefore, the timing signal 22a (zero justification) assumes a low level at the time slots 50, 52, while the signal 22b (negative justification) a low level only at the time slot 50. On the other hand, the timing signal 22c (positive justification) takes a low level at the time slots 50, 52 and 54. While the timing signals 22a-22c assume the low levels, the clock CLK is blocked by the pointer offset generator 22. It is therefore understood that the clocks 24a-24c exhibit the illustrated waveforms.
In the following it is assumed that: (a) the justification status signal 26a indicates the zero justification (indicated by "0") during time points T1-T2 and the positive justification (indicated by "+") after T2 and, (b) the pointer value signal 28a indicates L both during T1-T2 and after T2.
In this case, the selector 16a selects the clock signal 24a (zero justification) during the time points T1-T2 and the clock signal 24c (positive justification) after the time point T2. The pointer offset counter 18a is supplied with the clock signals selected by the selector 16a and counts the clocks. It is further assumed that the output 19a of the counter 18a indicates the counted values (viz., . . . , L-1, L, L+1, . . . ) as shown in FIG. 2. Thus, the comparator 20a detects the coincidence of the signals 19a, 28a at time slots TS1, TS2 and outputs pulses H during TS1, TS2 each of which indicates the location of the byte where the data (e.g., virtual container) begins.
The above mentioned prior art technique, however, suffers from the drawback in that all the channels should be provided with the pointer offset counters (18a-18c in the above case). In the case where a large number of channels are necessary, a bulky, complicate and expensive arrangement inevitably results.